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ad9200 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a complete 10-bit, 20 msps, 80 mw cmos a/d converter functional block diagram a/d a/d ain reftf refbf refsense otr d9 (msb) d0 (lsb) vref drvdd avdd clk drvss ad9200 sha sha sha gain sha gain gain d/a a/d d/a a/d d/a correction logic output buffers refts 1v avss refbs three- state mode stby clamp clamp in sha gain a/d d/a features cmos 10-bit, 20 msps sampling a/d converter pin-compatible with ad876 power dissipation: 80 mw (3 v supply) operation between 2.7 v and 5.5 v supply differential nonlinearity: 0.5 lsb power-down (sleep) mode three-state outputs out-of-range indicator built-in clamp function (dc restore) adjustable on-chip voltage reference if undersampling to 135 mhz product description the ad9200 is a monolithic, single supply, 10-bit, 20 msps analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. the ad9200 uses a multistage differential pipeline architecture at 20 msps data rates and guarantees no missing codes over the full operating temperature range. the input of the ad9200 has been designed to ease the devel- opment of both imaging and communications systems. the user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially. the sample-and-hold (sha) amplifier is equally suited for both multiplexed systems that switch full-scale voltage levels in suc- cessive channels and sampling single-channel inputs at frequen- cies up to and beyond the nyquist rate. ac coupled input signals can be shifted to a predetermined level, with an onboard clamp circuit (AD9200ARS, ad9200kst). the dynamic per- formance is excellent. the ad9200 has an onboard programmable reference. an external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. a single clock input is used to control all internal conversion cycles. the digital output data is presented in straight binary output format. an out-of-range signal (otr) indicates an over- flow condition which can be used with the most significant bit to determine low or high overflow. the ad9200 can operate with supply range from 2.7 v to 5.5 v, ideally suiting it for low power operation in high speed portable applications. the ad9200 is specified over the industrial (C40 c to +85 c) and commercial (0 c to +70 c) temperature ranges. product highlights low power the ad9200 consumes 80 mw on a 3 v supply (excluding the reference power). in sleep mode, power is reduced to below 5 mw. very small package the ad9200 is available in both a 28-lead ssop and 48-lead lqfp packages. pin compatible with ad876 the ad9200 is pin compatible with the ad876, allowing older designs to migrate to lower supply voltages. 300 mhz on-board sample-and-hold the versatile sha input can be configured for either single- ended or differential inputs. out-of-range indicator the otr output bit indicates when the input signal is beyond the ad9200s input range. built-in clamp function allows dc restoration of video signals with AD9200ARS and ad9200kst.
C2C rev. e ad9200Cspecifications (avdd = +3 v, drvdd = +3 v, f s = 20 mhz (50% duty cycle), mode = avdd, 2 v input span from 0.5 v to 2.5 v, external reference, t min to t max unless otherwise noted) parameter symbol min typ max units condition resolution 10 bits conversion rate f s 20 mhz dc accuracy differential nonlinearity dnl 0.5 1 lsb refts = 2.5 v, refbs = 0.5 v integral nonlinearity inl 0.75 2 lsb offset error e zs 0.4 1.2 % fsr gain error e fs 1.4 3.5 % fsr reference voltages top reference voltage refts 1 avdd v bottom reference voltage refbs gnd avdd C 1 v differential reference voltage 2 v p-p reference input resistance 1 10 k w refts, refbs: mode = avdd 4.2 k w between reftf and refbf: mode = avss analog input input voltage range ain refbs refts v refbs min = gnd: refts max = avdd input capacitance c in 1 pf switched aperture delay t ap 4ns aperture uncertainty (jitter) t aj 2ps input bandwidth (C3 db) bw full power (0 db) 300 mhz dc leakage current 23 m a input = fs internal reference output voltage (1 v mode) vref 1 v refsense = vref output voltage tolerance (1 v mode) 10 25 mv output voltage (2 v mode) vref 2 v refsense = gnd load regulation (1 v mode) 0.5 2 mv 1 ma load current power supply operating voltage avdd 2.7 3 5.5 v drvdd 2.7 3 5.5 v supply current iavdd 26.6 33.3 ma avdd = 3 v, mode = avss power consumption p d 80 100 mw avdd = drvdd = 3 v, mode = avss power-down 4 mw stby = avdd, mode and clock = avss gain error power supply rejection psrr 1 % fs dynamic performance (ain = 0.5 dbfs) signal-to-noise and distortion sinad f = 3.58 mhz 54.5 57 db f = 10 mhz 54 db effective bits f = 3.58 mhz 9.1 bits f = 10 mhz 8.6 bits signal-to-noise snr f = 3.58 mhz 55 57 db f = 10 mhz 56 db total harmonic distortion thd f = 3.58 mhz C59 C66 db f = 10 mhz C58 db spurious free dynamic range sfdr f = 3.58 mhz C61 C69 db f = 10 mhz C61 db two-tone intermodulation distortion imd 68 db f = 44.49 mhz and 45.52 mhz differential phase dp 0.1 degree ntsc 40 ire mod ramp differential gain dg 0.05 %
parameter symbol min typ max units condition digital inputs high input voltage v ih 2.4 v low input voltage v il 0.3 v digital outputs high-z leakage i oz C10 +10 m a output = gnd to vdd data valid delay t od 25 ns c l = 20 pf data enable delay t den 25 ns data high-z delay t dhz 13 ns logic output (with drvdd = 3 v) high level output voltage (i oh = 50 m a) v oh +2.95 v high level output voltage (i oh = 0.5 ma) v oh +2.80 v low level output voltage (i ol = 1.6 ma) v ol +0.4 v low level output voltage (i ol = 50 m a) v ol +0.05 v logic output (with drvdd = 5 v) high level output voltage (i oh = 50 m a) v oh +4.5 v high level output voltage (i oh = 0.5 ma) v oh +2.4 v low level output voltage (i ol = 1.6 ma) v ol +0.4 v low level output voltage (i ol = 50 m a) v ol +0.1 v clocking clock pulsewidth high t ch 22.5 ns clock pulsewidth low t cl 22.5 ns pipeline latency 3 cycles clamp 2 clamp error voltage e oc 20 40 mv clampin = 0.5 vC2.7 v, r in = 10 w clamp pulsewidth t cpw 2 m sc in = 1 m f (period = 63.5 m s) notes 1 see figures 1a and 1b. 2 available only in AD9200ARS and ad9200kst. specifications subject to change without notice. ad9200 refts refbs mode av dd 10k v 10k v 0.4 3 v dd ad9200 refts refbf mode reftf refbs 4.2k v figure 1a. figure 1b. ad9200 C3C rev. e
ad9200 C4C rev. e drvdd avss drvss drvss avdd avdd avss avss avdd reftf refts avdd avss avdd avss refbs refbf avdd avss avdd avss avdd avss avdd avss avss avdd avss avdd avdd avss avdd avss avdd avss absolute maximum ratings* with respect parameter to min max units avdd avss C0.3 +6.5 v drvdd drvss C0.3 +6.5 v avss drvss C0.3 +0.3 v avdd drvdd C6.5 +6.5 v mode avss C0.3 avdd + 0.3 v clk avss C0.3 avdd + 0.3 v digital outputs drvss C0.3 drvdd + 0.3 v ain avss C0.3 avdd + 0.3 v vref avss C0.3 avdd + 0.3 v refsense avss C0.3 avdd + 0.3 v reftf, reftb avss C0.3 avdd + 0.3 v refts, refbs avss C0.3 avdd + 0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature 10 sec +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. ordering guide temperature package package model range description options* ad9200jrs 0 c to +70 c 28-lead ssop rs-28 AD9200ARS C40 c to +85 c 28-lead ssop rs-28 ad9200jst 0 c to +70 c 48-lead lqfp st-48 ad9200kst 0 c to +70 c 48-lead lqfp st-48 ad9200jrsrl 0 c to +70 c 28-lead ssop (reel) rs-28 AD9200ARSrl C40 c to +85 c 28-lead ssop (reel) rs-28 ad9200jstrl 0 c to +70 c 48-lead lqfp (reel) st-48 ad9200kstrl 0 c to +70 c 48-lead lqfp (reel) st-48 ad9200 ssop-eval evaluation board ad9200 lqfp-eval evaluation board *rs = shrink small outline; st = thin quad flatpack. figure 2. equivalent circuits a. d0Cd9, otr b. three-state, standby, clamp c. clk d. ain e. reference f. clampin g. mode h. refsense i. vref caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9200 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad9200 C5C rev. e pin configurations pin function descriptions ssop lqfp pin no. pin no. name description 1 44 avss analog ground 2 45 drvdd digital driver supply 3 1 d0 bit 0, least significant bit 4 2 d1 bit 1 5 3 d2 bit 2 6 4 d3 bit 3 7 5 d4 bit 4 8 8 d5 bit 5 9 9 d6 bit 6 10 10 d7 bit 7 11 11 d8 bit 8 12 12 d9 bit 9, most significant bit 13 16 otr out-of-range indicator 14 17 drvss digital ground 15 22 clk clock input 16 23 three-state hi: high impedance state. lo: normal operation 17 24 stby hi: power-down mode. lo: normal operation 18 26 refsense reference select 19 27 clamp hi: enable clamp mode. lo: no clamp 20 28 clampin clamp reference input 21 29 refts top reference 22 30 reftf top reference decoupling 23 32 mode mode select 24 34 refbf bottom reference decoupling 25 35 refbs bottom reference 26 38 vref internal reference output 27 39 ain analog input 28 42 avdd analog supply 28-lead shrink small outline (ssop) 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad9200 avss refbs vref ain avdd drvdd d0 d1 reftf mode refbf d2 d3 d4 d5 d6 d7 clamp clampin refts d8 d9 otr drvss refsense clk three-state stby 48-lead plastic thin quad flatpack (lqfp) 36 35 34 33 32 31 30 29 28 27 26 25 avdd vref nc nc nc avss nc nc ain nc 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) nc refbs refbf nc mode nc reftf nc nc nc nc otr drvss nc d0 d1 d2 d3 d4 nc nc nc = no connect d5 d6 d7 d8 refts clampin clamp refsense nc nc clk three-state nc ad9200 stby d9 nc drvdd
ad9200 C6C rev. e definitions of specifications integral nonlinearity (inl) integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. the point used as zero occurs 1/2 lsb before the first code transi- tion. full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the center of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. it is often specified in terms of the resolution for which no missing codes (nmc) are guaranteed. typical characterization curves code offset 1.0 0.5 ?.0 0 1024 128 dnl 256 384 512 640 768 896 0 ?.5 figure 3. typical dnl code offset 1.0 0.5 ?.0 0 1024 128 inl 256 384 512 640 768 896 0 ?.5 figure 4. typical inl offset error the first transition should occur at a level 1 lsb above zero. offset is defined as the deviation of the actual first code transi- tion from that point. gain error the first code transition should occur for an analog value 1 lsb above nominal negative full scale. the last transition should occur for an analog value 1 lsb below the nominal positive full scale. gain error is the deviation of the actual difference be- tween first and last code transitions and the ideal difference between the first and last code transitions. pipeline delay (latency) the number of clock cycles between conversion initiation and the associated output data being made available. new output data is provided every rising edge. input frequency ?hz 60 55 20 1.00e+05 1.00e+08 1.00e+06 1.00e+07 50 45 25 40 35 30 snr?db ?.5 amplitude ?.0 amplitude ?0.0 amplitude figure 5. snr vs. input frequency 60 55 20 1.00e+05 1.00e+08 1.00e+06 sinad ?db 1.00e+07 50 45 25 40 35 30 ?.5 amplitude ?.0 amplitude ?0.0 amplitude input frequency ?hz figure 6. sinad vs. input frequency (avdd = +3 v, drvdd = +3 v, f s = 20 mhz (50% duty cycle), mode = avdd, 2 v input span from 0.5 v to 2.5 v, external reference, unless otherwise noted)
ad9200 C7C rev. e ?0 ?5 ?0 1.00e+05 1.00e+08 1.00e+06 1.00e+07 ?0 ?5 ?5 ?0 ?5 thd ?db ?0 ?.5 amplitude ?.0 amplitude ?0.0 amplitude input frequency ?hz ?0 ?5 clock = 20mhz figure 7. thd vs. input frequency clock frequency ?hz ?0 ?0 0 100e+03 100e+06 1e+06 thd ?db 10e+06 ?0 ?0 ?0 ?0 ?0 f in = 1mhz figure 8. thd vs. clock frequency temperature ? c 1.005 1.004 0.998 ?0 100 ?0 v ref ?v 0 1.003 1.002 0.999 1.001 1.000 20 40 60 80 figure 9. voltage reference error vs. temperature clock frequency ?mhz 80.5 80.0 77.0 020 2 power consumption ?mw 4 79.5 79.0 77.5 78.5 78.0 6 8 10 12 14 16 18 clock frequency ?mhz 80.5 80.0 77.0 020 2 power consumption ?mw 4 79.5 79.0 77.5 78.5 78.0 6 8 10 12 14 16 18 figure 10. power consumption vs. clock frequency (mode = avss) 1m 900k 0 nC1 n hits n+1 800k 700k 100k 400k 300k 200k code 600k 500k 499856 54383 54160 figure 11. grounded input histogram single tone frequency domain 20 ?0 ?40 0e+0 10e+6 1e+6 2e+6 3e+6 4e+6 5e+6 6e+6 7e+6 8e+6 9e+6 0 ?0 ?00 ?20 ?0 ?0 clock = 20mhz figure 12. single-tone frequency domain
ad9200 C8C rev. e table i. mode selection input input mode refsense modes connect span pin pin ref refts refbs figure top/bottom ain 1 v avdd short refsense, refts and vref together agnd 18 ain 2 v avdd agnd short refts and vref together agnd 19 center span ain 1 v avdd/2 short vref and refsense together avdd/2 avdd/2 20 ain 2 v avdd/2 agnd no connect avdd/2 avdd/2 differential ain is input 1 1 v avdd/2 short vref and refsense together avdd/2 avdd/2 29 refts and refbs are shorted together for input 2 2 v avdd/2 agnd no connect avdd/2 avdd/2 external ref ain 2 v max avdd avdd no connect span = refts 21, 22 C refbs (2 v max) agnd short to short to 23 vreftf vrefbf ad876 ain 2 v float or avdd no connect short to short to 30 avss vreftf vrefbf 0 ? 1.0e+6 1.0e+9 10.0e+6 signal amplitude ?db 100.0e+6 ? ? frequency ?hz ?2 ?5 ?8 ?1 ?4 ?7 figure 13. full power bandwidth 25 20 C25 0 3.0 1.0 2.0 15 10 C5 C10 C15 input voltage C v 5 0 C20 2.5 0.5 1.5 i b C m a refbs = 0.5v refts = 2.5v clock = 20mhz figure 14. input bias current vs. input voltage applying the ad9200 theory of operation the ad9200 implements a pipelined multistage architecture to achieve high sample rate with low power. the ad9200 distrib- utes the conversion over several smaller a/d subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. as a consequence of the distrib- uted conversion, the ad9200 requires a small fraction of the 1023 comparators used in a traditional flash type a/d. a sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the second, third and fourth stages operate on the three preceding samples. operational modes the ad9200 is designed to allow optimal performance in a wide variety of imaging, communications and instrumentation applications, including pin compatibility with the ad876 a/d. to realize this flexibility, internal switches on the ad9200 are used to reconfigure the circuit into different modes. these modes are selected by appropriate pin strapping. there are three parts of the circuit affected by this modality: the voltage reference, the reference buffer, and the analog input. the nature of the appli- cation will determine which mode is appropriate: the descrip- tions in the following sections, as well as the table i should assist in picking the desired mode.
ad9200 C9C rev. e summary of modes voltage reference 1 v mode the internal reference may be set to 1 v by connect- ing refsense and vref together. 2 v mode the internal reference my be set to 2 v by connecting refsense to analog ground external divider mode the internal reference may be set to a point between 1 v and 2 v by adding external resistors. see figure 16f. external reference mode enables the user to apply an exter- nal reference to refts, refbs and vref pins. this mode is attained by tying refsense to vdd. reference buffer center span mode midscale is set by shorting refts and refbs together and applying the midscale voltage to that point the mode pin is set to avdd/2. the analog input will swing about that midscale point. top/bottom mode sets the input range between two points. the two points are between 1 v and 2 v apart. the top/bottom mode is enabled by tying the mode pin to avdd. analog input differential mode is attained by driving the ain pin as one differential input and shorting refts and refbs together and driving them as the second differential input. the mode pin is tied to avdd/2. preferred mode for optimal distortion performance. single-ended is attained by driving the ain pin while the refts and refbs pins are held at dc points. the mode pin is tied to avdd. single-ended/clamped (ac coupled) the input may be clamped to some dc level by ac coupling the input. this is done by tying the clampin to some dc point and applying a pulse to the clamp pin. mode pin is tied to avdd. special ad876 mode enables users of the ad876 to drop the ad9200 into their socket. this mode is attained by floating or grounding the mode pin. input and reference overview figure 16, a simplified model of the ad9200, highlights the relationship between the analog input, ain, and the reference voltages, refts, refbs and vref. like the voltages applied to the resistor ladder in a flash a/d converter, refts and refbs define the maximum and minimum input voltages to the a/d. the input stage is normally configured for single-ended opera- tion, but allows for differential operation by shorting refts and refbs together to be used as the second input. sha ain refts refbs a/d core ad9200 figure 15. ad9200 equivalent functional input circuit in single-ended operation, the input spans the range, refbs ain refts where refbs can be connected to gnd and refts con- nected to vref. if the user requires a different reference range, refbs and refts can be driven to any voltage within the power supply rails, so long as the difference between the two is between 1 v and 2 v. in differential operation, refts and refbs are shorted to- gether, and the input span is set by vref, ( refts C vref/2 ) ain ( refts + vref/2 ) where vref is determined by the internal reference or brought in externally by the user. the best noise performance may be obtained by operating the ad9200 with a 2 v input range. the best distortion perfor- mance may be obtained by operating the ad9200 with a 1 v input range. reference operation the ad9200 can be configured in a variety of reference topolo- gies. the simplest configuration is to use the ad9200s onboard bandgap reference, which provides a pin-strappable option to generate either a 1 v or 2 v output. if the user desires a refer- ence voltage other than those two, an external resistor divider can be connected between vref, refsense and analog ground to generate a potential anywhere between 1 v and 2 v. another al ternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. a third alternative is to bring in top and bottom references, bypassing vref altogether. figures 16d, 16e and 16f illustrate the reference and input ar- chitecture of the ad9200. in tailoring a desired arrangement, the user can select an input configuration to match drive circuit. then, m oving to the reference modes at the bottom of the figure, select a reference circuit to accommodate the offset and amplitude of a full-scale signal. table i outlines pin configurations to match user requirements.
ad9200 C10C rev. e sha a2 10k v 10k v 10k v a/d core 4.2k v total refts refbs 10 m f 0.1 m f reftf refbf 0.1 m f ain +f/s range obtained from vref pin or external ref Cf/s range obtained from vref pin or external ref 0.1 m f mode (avdd) +fs Cfs ad9200 10k v a. top/bottom mode v maximum magnitude of v is determined by internal reference and turns ratio mode internal ref avdd/2 sha 10k v 10k v 10k v a/d core 4.2k v total 10 m f 0.1 m f reftf refbf 0.1 m f ain 0.1 m f ad9200 10k v a2 refts refbs avdd/2 c. differential mode a1 1v avss refsense vref (1v) ad9200 0.1 m f 1.0 m f d. 1 v reference 0.01 m f 1.0 m f a1 10k v 10k v 1v avss refsense vref (2v) ad9200 e. 2 v reference a1 1v avss refsense vref (= 1 + r a /r b ) r a r b internal 10k ref resistors are switched open by the presense of r a and r b . ad9200 0.1 m f 1.0 m f f. variable reference (between 1 v and 2 v) figure 16. a1 1v refsense avdd vref ad9200 g. internal reference disable (power reduction) mode internal ref midscale offset voltage is derived from internal or external ref midscale v* avdd/2 * maximum magnitude of v is determined by internal reference 10k v 10k v 10k v a/d core 4.2k v total refts refbs 10 m f 0.1 m f reftf refbf 0.1 m f ain 0.1 m f ad9200 10k v a2 sha b. center span mode
ad9200 C11C rev. e the actual reference voltages used by the internal circuitry of the ad9200 appear on reftf and refbf. for proper opera- tion, it is necessary to add a capacitor network to decouple these pins. the reftf and refbf should be decoupled for all internal and external configurations as shown in figure 17. ad9200 reftf refbf 0.1 m f 0.1 m f 10 m f 0.1 m f figure 17. reference decoupling network note: reftf = reference top, force refbf = reference bottom, force refts = reference top, sense refbs = reference bottom, sense internal reference operation figures 18, 19 and 20 show example hookups of the ad9200 internal reference in its most common configurations. (figures 18 and 19 illustrate top/bottom mode while figure 20 illustrates center span mode). figure 29 shows how to connect the ad9200 for 1 v p-p differ ential operation. shorting the vref pin directly to the refsense pin places the internal reference amplifier, a1, in unity-gain mode and the resultant reference output is 1 v. in figure 18 refbs is grounded to give an input range from 0 v to 1 v. these modes can be chosen when the supply is ei ther +3 v or +5 v. the vref pin must be bypassed to avss (analog ground) with a 1.0 m f tantalum capacitor in parallel with a low inductance, low esr, 0.1 m f ceramic capacitor. 1v 0v mode avdd 10k v 10k v 10k v a/d core 4.2k v total refts refbs 10 m f 0.1 m f reftf refbf 0.1 m f ain 0.1 m f ad9200 10k v ref sense vref a1 1v a2 sha 0.1 m f 1.0 m f figure 18. internal reference 1 v p-p input span (top/bottom mode) figure 19 shows the single-ended configuration for 2 v p-p operation. refsense is connected to gnd, resulting in a 2 v reference output. 2v 0v mode avdd a2 10k v 10k v 10k v a/d core 4.2k v total refts refbs 10 m f 0.1 m f reftf refbf 0.1 m f ain 0.1 m f ad9200 10k v ref sense vref a1 1v sha 0.1 m f 1.0 m f figure 19. internal reference, 2 v p-p input span (top/bottom mode) figure 20 shows the single-ended configuration that gives the good high frequency dynamic performance (sinad, sfdr). to optimize dynamic performance, center the common-mode voltage of the analog input at approximately 1.5 v. connect the shorted refts and refbs inputs to a low impedance 1.5 v source. in this configuration, the mode pin is driven to a volt- age at midsupply (avdd/2). maximum reference drive is 1 ma. an external buffer is re- quired for heavier loads. avdd/2 +1.5v 2v 1v mode 10k v 10k v 10k v a/d core 4.2k v total refts refbs 10 m f 0.1 m f reftf refbf 0.1 m f ain 0.1 m f ad9200 10k v ref sense vref 1v sha a2 a1 0.1 m f 1.0 m f figure 20. internal reference 1 v p-p input span, (center span mode)
ad9200 C12C rev. e external reference operation using an external reference may provide more flexibility and improve drift and accuracy. figures 21 through 23 show ex- amples of how to use an external reference with the ad9200. to use an external reference, the user must disable the internal reference amplifier by connecting the refsense pin to vdd. the user then has the option of driving the vref pin, or driv- ing the refts and refbs pins. the ad9200 contains an internal reference buffer (a2), that simplifies the drive requirements of an external reference. the external reference must simply be able to drive a 10 k w load. figure 21 shows an example of the user driving the top and bottom references. refts is connected to a low impedance 2 v source and refbs is connected to a low impedance 1 v source. refts and refbs may be driven to any voltage within the supply as long as the difference between them is between 1 v and 2 v. 2v 1v avdd 2v 1v mode a2 10k v 10k v 10k v a/d core 4.2k v total refts refbs 10 m f 0.1 m f reftf refbf 0.1 m f ain 0.1 m f ad9200 10k v ref sense sha figure 21. external reference mode1 v p-p input span figure 22 shows an example of an external reference generating 2.5 v at the shorted refts and refbs inputs. in this in- stance, a ref43 2.5 v reference drives refts and refbs. a resistive divider generates a 1 v vref signal that is buffered by a3. a3 must be able to drive a 10 k w , capacitive load. choose this op amp based on noise and accuracy requirements. 3.0v 2.0v 2.5v avdd ain refts reftf refbf refbs vref refsense mode ad9200 0.1 m f a3 1.5k v 1k v 10 m f 0.1 m f ref43 +5v 0.1 m f 0.1 m f 10 m f avdd 1.0 m f 0.1 m f avdd 0.1 m f 0.1 m f avdd/2 figure 22. external reference mode1 v p-p input span 2.5 v cm figure 23a shows an example of the external references driving the reftf and refbf pins that is compatible with the ad876. refts is shorted to reftf and driven by an external 4 v low impedance source. refbs is shorted to refbf and driven by a 2 v source. the mode pin is connected to gnd in this configuration. 4v 2v 0.1 f 0.1 f avdd 10 f 0.1 f 4v 2v vin refts reftf refbf refbs vref refsense mode ad9200 figure 23a. external reference2 v p-p input span 6 5 8 7 +5v c3 0.1 f c4 0.1 f refts reftf c2 10 f c6 0.1 f 2 3 6 c5 0.1 f refbs refbf 4 c1 0.1 f ad9200 reft refb figure 23b. kelvin connected reference using the ad9200 standby operation the adc may be placed into a powered down (sleep) mode by driving the stby (standby) pin to logic high potential and holding the clock at logic low. in this mode the typical power drain is approximately 4 mw. if there is no connection to the stby pin, an internal pull-down circuit will keep the adc in a wake-up mode of operation. the adc will wake up in 400 ns (typ) after the standby pulse goes low. clamp operation the AD9200ARS and ad9200kst parts feature an optional clamp circuit for dc restoration of video or ac coupled signals. figure 24 shows the internal clamp circuitry and the external control signals needed for clamp operation. to enable the clamp, apply a logic high to the clamp pin. this will close the switch sw1. the clamp amplifier will then servo the volt- age at the ain pin to be equal to the clamp voltage applied at the clampin pin. after the desired clamp level is attained, sw1 is opened by taking clamp back to a logic low. ignoring the droop caused by the input bias current, the input capacitor cin will hold the dc voltage at ain constant until the next clamp interval. the input resistor rin has a minimum recom- mended value of 10 w , to maintain the closed-loop stability of the clamp amplifier. the allowable voltage range that can be applied to clampin depends on the operational limits of the internal clamp ampli- fier. when operating off of 3 volt supplies, the recommended clamp range is between 0.5 volts and 2.0 volts.
ad9200 C13C rev. e the input capacitor should be sized to allow sufficient acquisi- tion time of the clamp voltage at ain within the clamp inter- val, but also be sized to minimize droop between clamping intervals. specifically, the acquisition time when the switch is closed will equal: t acq = r in c in ln v c v e ? ? ? ? where v c is the voltage change required across c in , and v e is the error voltage. v c is calculated by taking the difference be- tween the initial input dc level at the start of the clamp interval and the clamp voltage supplied at clampin. v e is a system- dependent parameter, and equals the maximum tolerable devia- tion from v c . for example, if a 2-volt input level needs to be clamped to 1 volt at the ad9200s input within 10 millivolts, then v c equals 2 C 1 or 1 volt, and v e equals 10 mv. note that once the proper clamp level is attained at the input, only a very small voltage change will be required to correct for droop. the voltage droop is calculated with the following equation: dv = i bias c in t () where t = time between clamping intervals. the bias current of the ad9200 will depend on the sampling rate, f s . the switched capacitor input ain appears resistive over time, with an input resistance equal to 1/c s f s . given a sampling rate of 20 msps and an input capacitance of 1 pf, the input resistance is 50 k w . this input resistance is equivalently terminated at the midscale voltage of the input range. the worst case bias current will thus result when the input signal is at the extremes of the input range, that is, the furthest distance from the midscale voltage level. for a 1-volt input range, the maxi- mum bias current will be 0.5 volts divided by 50 k w , which is 10 m a. if droop is a critical parameter, then the minimum value of c in should be calculated first based on the droop requirement. acquisition timethe width of the clamp pulsecan be adjusted accordingly once the minimum capacitor value is cho- sen. a tradeoff will often need to be made between droop and acquisition time, or error voltage v e . clamp circuit example a single supply video amplifier outputs a level-shifted video signal between 2 and 3 volts with the following parameters: horizontal period = 63.56 m s, horizontal sync interval = 10.9 m s, horizontal sync pulse = 4.7 m s, sync amplitude = 0.3 volts, video amplitude of 0.7 volts, reference black level = 2.3 volts the video signal must be dc restored from a 2- to 3-volt range down to a 1- to 2-volt range. c onfiguring the ad9200 for a one volt input span with an input range from 1 to 2 v olts (see figure 24), the clampin voltage can be set to 1 volt with an external voltage or by direct connection to refbs. the clamp pulse may be applied during the sync pulse, or during the back porch to truncate the sync below the ad9200s mini- mum input voltage. with a c in = 1 m f, and r in = 20 w , the acqui sition time needed to set the input dc level to one volt with 1 mv accuracy is about 140 m s, assuming a full 1 volt v c . with a 1 m f input coupling capacitor, the droop across one horizontal can be calculated: i bias = 10 m a, and t = 63.5 m s, so dv = 0.635 mv, which is less than one lsb. after the input capacitor is initially charged, the clamp pulse- width only needs to be wide enough to correct small voltage errors such as the droop. the fine scale settling characteristics of the clamp circuitry are shown in table ii. depend ing on the required accuracy, a clamp pulsewidth of 1 m sC3 m s should work in most applications. the offset val- ues ignore the contribution of offset from the clamp amplifier; they simply compare the output code with a final value mea- sured with a much longer clamp pulse duration. table ii. clamp offset 10 m s <1 lsb 5 m s 5 lsbs 4 m s 7 lsbs 3 m s 11 lsbs 2 m s 19 lsbs 1 m s 42 lsbs clamp in ad9200 clamp ain cin rin to sha sw1 figure 24a. clamp operation 0.1 f 10 f ain reftf refbs mode ad9200 refts 0.1 f refbf clamp clampin avdd 2 short to refbs or external dc 0.1 f figure 24b. video clamp circuit
ad9200 C14C rev. e driving the analog input figure 25 shows the equivalent analog input of the ad9200, a sample-and-hold amplifier (switched capacitor input sha). bringing clk to a logic low level closes switches 1 and 2 and opens switch 3. the input source connected to ain must charge capacitor ch during this time. when clk transitions from logic low to logic high, switches 1 and 2 open, placing the sha in hold mode. switch 3 then closes, forcing the output of the op amp to equal the voltage stored on ch. when clk transitions from logic high to logic low, switch 3 opens first. switches 1 and 2 close, placing the sha in track mode. the structure of the input sha places certain requirements on the input drive source. the combination of the pin capacitance, cp, and the hold capacitance, ch, is typically less than 5 pf. the input source must be able to charge or discharge this ca- pacitance to 10-bit accuracy in one half of a clock cycle. when the sha goes into track mode, the input source must charge or discharge capacitor ch from the voltage already stored on ch to the new voltage. in the worst case, a full-scale voltage step on the input, the input source must provide the charging current through the r on (50 w ) of switch 1 and quickly (within 1/2 clk period) settle. this situation corresponds to driving a low input impedance. on the other hand, when the source voltage equals the value previously stored on ch, the hold capacitor requires no input current and the equivalent input impedance is ex- tremely high. adding series resistance between the output of the source and the ain pin reduces the drive requirements placed on the source. figure 26 shows this configuration. the bandwidth of the particular application limits the size of this resistor. to maintain the performance outlined in the data sheet specifica- tions, the resistor should be limited to 20 w or less. for applica- tions with signal bandwidths less than 10 mhz, the user may proportionally increase the size of the series resistor. alterna- tively, adding a shunt capacitance between the ain pin and analog ground can lower the ac load impedance. the value of this capacitance will depend on the source resistance and the required signal bandwidth. the input span of the ad9200 is a function of the reference voltages. for more information regarding the input range, see the internal and external reference sections of the data sheet. ch ch cp cp s1 s3 s2 ain (refts refbs) sha ad9200 figure 25. ad9200 equivalent input structure ain v s < 20 v ad9200 figure 26. simple ad9200 drive configuration in many cases, particularly in single-supply operation, ac cou- pling offers a convenient way of biasing the analog input signal at the proper signal range. figure 25 shows a typical configura- tion for ac-coupling the analog input signal to the ad9200. maintaining the specifications outlined in the data sheet requires careful selection of the component values. the most important is the f C3 db high-pass corner frequency. it is a function of r2 and the parallel combination of c1 and c2. the f C3 db point can be approximated by the equation: f C3 db = 1/(2 pi [ r 2] c eq ) where c eq is the parallel combination of c1 and c2. note that c1 is typically a large electrolytic or tantalum capacitor that becomes inductive at high frequencies. adding a small ceramic or polystyrene capacitor (on the order of 0.01 m f) that does not become inductive until negligibly higher frequencies, maintains a low impedance over a wide frequency range. note: ac coupled input signals may also be shifted to a desired level with the ad9200s internal clamp. see clamp operation. ain r1 ad9200 i b r2 v bias c1 c2 v in figure 27. ac coupled input there are additional considerations when choosing the resistor values. the ac-coupling capacitors integrate the switching tran- sients present at the input of the ad9200 and cause a net dc bias current, i b , to flow into the input. the magnitude of the bias current in creases as the signal magnitude deviates from v midscale and the clock frequency increases; i.e., minimum bias current flow when ain = v midscale. this bias current will re sult in an offset error of (r1 + r2) i b . if it is necessary to compensate this error, consider making r2 negligibly small or modifying vbias to account for the resultant offset. in systems that must use dc coupling, use an op amp to level- shift a ground-referenced signal to comply with the input re- quirements of the ad9200. figure 28 shows an ad8041 config- ured in noninverting mode. ain 20 ad9200 6 7 2 3 4 nc 0.1 f +v cc nc midscale offset voltage 0v dc 1v p-p ad8041 5 1 figure 28. bipolar level shift
ad9200 C15C rev. e differential input operation the ad9200 will accept differential input signals. this function may be used by shorting refts and refbs and driving them as one leg of the differential signal (the top leg is driven into ain). in the configuration below, the ad9200 is accepting a 1 v p-p signal. see figure 29. ain refts reftf refbf refbs ad9200 0.1 m f 10 m f 0.1 m f 0.1 m f 2v 1v avdd/2 vref refsense mode avdd/2 0.1 m f 1.0 m f figure 29. differential input ad876 mode of operation the ad9200 may be dropped into the ad876 socket. this will allow a d876 users to take advantage of the reduced power consumption realized when running the ad9200 on a 3.0 v analog supply. figure 30 shows the pin functions of the ad876 and ad9200. the grounded refsense pin and floating mode pin effec- tively put the ad9200 in the external reference mode. the external reference input for the ad876 will now be placed on the reference pins of the ad9200. the clamp controls will be grounded by the ad876 socket. the ad9200 has a 3 clock cycle delay compared to a 3.5 cycle delay of the ad876. 4v 2v 0.1 m f 0.1 m f avdd 10 m f 0.1 m f 4v 2v ain refts reftf refbf refbs clamp refsense ad9200 mode nc clampin otr vref 0.1 m f figure 30. ad876 mode clock input the ad9200 clock input is buffered internally with an inverter powered from the avdd pin. this feature allows the ad9200 to accommodate either +5 v or +3.3 v cmos logic input sig- nal swings with the input threshold for the clk pin nominally at avdd/2. the pipelined architecture of the ad9200 operates on both rising and falling edges of the input clock. to minimize duty cycle variations the recommended logic family to drive the clock input is high speed or advanced cmos (hc/hct, ac/act) logic. cmos logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 20 msps operation. the ad9200 is designed to support a conversion rate of 20 msps; running the part at slightly faster clock rates may be possible, although at reduced performance levels. con versely, some slight performance improvements might be realized by clocking the ad9200 at slower clock rates. t cl t ch t c 25ns data 1 data output input clock analog input s1 s2 s3 s4 figure 31. timing diagram the power dissipated by the output buffers is largely propor- tional to the clock frequency; running at reduced clock rates provides a reduction in power consumption. digital inputs and outputs each of the ad9200 digital control inputs, three-state and stby are reference to analog ground. the clock is also referenced to analog ground. the format of the digital output is straight binary (see figure 32). a low power mode feature is provided such that for stby = high and the clock disabled, the static power of the ad9200 will drop below 5 mw. otr Cfs Cfs+1lsb +fsC1lsb +fs figure 32. output data format high impedance t dhz t den three- state data (d0?9) figure 33. three-state timing diagram
ad9200 C16C rev. e applications direct if down conversion using the ad9200 sampling if signals above an adcs baseband region (i.e., dc to f s /2) is becoming increasingly popular in communication applications. this process is often referred to as direct if down conversion or undersampling. there are several potential ben- efits in using the adc to alias (i.e., or mix) down a narrowband or wideband if signal. first and foremost is the elimination of a complete mixer stage with its associated amplifiers and filters, reducing cost and power dissipation. second is the ability to apply various dsp techniques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, detection, etc. a detailed discussion on using this technique in digital receivers can be found in analog devices application notes an-301 and an-302. in direct if down conversion applications, one exploits the inherent sampling process of an adc in which an if signal lying outside the baseband region can be aliased back into the baseband region in a similar manner that a mixer will down- convert an if signal. similar to the mixer topology, an image rejection filter is required to limit other potential interfering signals from also aliasing back into the adcs baseband region. a tradeoff exists between the complexity of this image rejection filter and the sample rate as well as dynamic range of the adc. the ad9200 is well suited for various narrowband if sampling applications. the ad9200s low distortion input sha has a full-power bandwidth extending to 300 mhz thus encompassing many popular if frequencies. a dnl of 0.5 lsb (typ) com- bined with low thermal input referred noise allows the ad9200 in the 2 v span to provide 60 db of snr for a baseband input sine wave. also, its low aperture jitter of 2 ps rms ensures minimum snr degradation at higher if frequencies. in fact, the ad9200 is capable of still maintaining 56 db of snr at an if of 135 mhz with a 1 v (i.e., 4 dbm) input span. note, although the ad9200 will typically yield a 3 to 4 db improvement in snr when con- figured for the 2 v span, the 1 v span provides the optimum full-scale distortion performance. furthermore, the 1 v span reduces the performance requirements of the input d river cir- cuitry and thus may be more practical for system im plementa- tion purposes. figure 34 shows a simplified schematic of the ad9200 config- ured in an if sampling application. to reduce the complexity of the digital demodulator in many quadrature demodulation ap- plications, the if frequency and/or sample rate are selected such that the bandlimited if signal aliases back into the center of the adcs baseband region (i.e., f s /4). for example, if an if sig- nal centered at 45 mhz is sampled at 20 msps, an image of this if signal will be aliased back to 5.0 mhz which corre- sponds to one quarter of the sample rate (i.e., f s /4). this demodulation technique typically reduces the complexity of the post digital demodulator asic which follows the adc. to maximize its distortion performance, the ad9200 is config- ured in the differential mode with a 1 v span using a transformer. the center tap of the transformer is biased at midsupply via a resistor divider. preceding the ad9200 is a bandpass filter as well as a 32 db gain stage. a large gain stage may be required to compensate for the high insertion losses of a saw filter used for image rejection. the gain stage will also provide adequate isolation for the saw filter from the charge kick back currents associated with ad9200s input stage. the gain stage can be realized using one or two cascaded ad8009 op amps amplifiers. the ad8009 is a low cost, 1 ghz, current-feedback op amp having a 3rd order intercept character- ized up to 250 mhz. a passive bandpass filter following the ad8009 attenuates its dominant 2nd order distortion products which would otherwise be aliased back into the ad9200s baseband region. also, it reduces any out-of-band noise which would also be aliased back due to the ad9200s noise band- width of 220+ mhz. note, the bandpass filters specifications are application dependent and will affect both the total distor- tion and noise performance of this circuit. the distortion and noise performance of an adc at the given if frequency is of particular concern when evaluating an adc for a narrowband if sampling application. both single-tone and dual-tone sfdr vs. amplitude are very useful in an assessing an adcs noise performance and noise contribution due to aper- ture jitter. in any application, one is advised to test several units of the same device under the same conditions to evaluate the given applications sensitivity to that particular device. 0.1 m f ain refts ad9200 refbs refsense vref avdd 200 v 1k v 1k v 50 v 93.1 v 280 v 50 v 22.1 v 200 v saw filter output 50 v bandpass filter g 1 = 20db g 2 = 12db l-c mini circuits t4 - 6t 1:4 0.1 m f 1.0 m f figure 34. simplified ad9200 if sampling circuit
ad9200 C17C rev. e figures 35C38 combine the dual-tone sfdr as well as single tone sfdr and snr performance at if frequencies of 45 mhz, 70 mhz, 85 mhz and 135 mhz. note, the sfdr vs. ampli- tude data is referenced to dbfs while the single tone snr data is referenced to dbc. the performance characteristics in these figures are representative of the ad9200 without the ad8009. the ad9200 was operated in the differential mode (via trans- former) with a 1 v span at 20 msps. the analog supply (avdd) and the digital supply (drvdd) were set to +5 v and 3.3 v, respectively. 90 80 0 ?0 0 ?0 ?0 70 60 30 20 input power level ?dbfs 50 40 10 ?0 ?0 ?0 worst case spurious ?dbfs snr ?dbc single tone sfdr dual tone sfdr snr clk = 20msps single tone ?45.52mhz dual tone ?f 1 = 44.49mhz ?f 2 = 45.52mhz figure 35. snr/sfdr for if @ 45 mhz 90 80 0 ?0 0 ?0 ?0 70 60 30 20 input power level ?dbfs 50 40 10 ?0 ?0 ?0 worst case spurious ?dbfs snr ?dbc single tone sfdr dual tone sfdr snr clk = 21.538msps single tone ?70.55mhz dual tone ?f 1 = 69.50mhz ?f 2 = 70.55mhz figure 36. snr/sfdr for if @ 70 mhz although not presented, data was also taken with the insertion of an ad8009 gain stage of 32 db in the signal path. no degra dation in two-tone sfdr vs. amplitude was noted at an if of 45 mhz, 70 mhz and 85 mhz. however, at 135 mhz, the ad8009 became the limiting factor in the distortion perfor- mance until the two input tones were decreased to C15 dbfs from their full-scale level of C6.5 dbfs. note: the snr perfor- mance in each case degraded by approximately 0.5 db due to the ad8009s in-band noise contribution. 90 80 0 ?0 0 ?0 ?0 70 60 30 20 input power level ?dbfs 50 40 10 ?0 ?0 ?0 worst case spurious ?dbfs snr ?dbc single tone sfdr dual tone sfdr snr clk = 20msps single tone ?85.52mhz dual tone ?f 1 = 84.49mhz ?f 2 = 85.52mhz figure 37. snr/sfdr for if @ 85 mhz worst case spurious C dbfs snr C dbc 90 80 0 C60 0 C40 C20 70 60 30 20 input power level C dbfs 50 40 10 C10 C50 C30 single tone sfdr dual tone sfdr snr clk = 20msps single tone C 135.52mhz dual tone C f 1 = 134.44mhz C f 2 = 135.52mhz figure 38. snr/sfdr for if @ 135 mhz
ad9200 C18C rev. e ad822 u2 u2 ad822 u3 ad822 u3 jp5 jp17 jp18 j7 gnd r53 49.9 v r37 1k v r38 1k v r39 1k v drvdd b s3 2 1 3 3 a 1 b 2 s4 a tp11 clamp three-state stby r14 10k v cw c9 10/10v +3C5a c10 0.1 m f 4 2 3 8 1 6 5 7 r18 316k v r16 1k v c29 0.1 m f q2 2n3904 c14 0.1 m f c15 10/10v tp17 extb r20 178 v r19 178 v c12 0.1 m f c13 10/10v cm tp16 extt q1 2n3906 0.626v to 4.8v r17 316 v r15 1k v c11 0.1 m f +3C5a 5 6 7 r13 11k v r12 10k v c8 10/10v c7 0.1 m f 8 1 4 2 3 +3C5a r10 5k v r11 15k v cw xxxx adj. tp14 r8 10k v r9 1.5k v d1 ad1580 +3C5a r7 5.49k v xxxx adj. dutclk three-state stby refsense clamp clampin refts reftf mode refbf refbs vref ain 1 14 c33 10/10v + ad9200 clk three-state stby refsense clamp clampin refts reftf mode refbf refbs vref ain d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 avss drvss avdd c17 10/10v avdd c16 0.1 m f c18 10/10v c19 0.1 m f drvdd 28 otr tp19 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 26 27 21 17 15 rn1 22 v rn1 22 v rn1 22 v rn1 22 v rn2 22 v rn2 22 v rn2 22 v rn1 22 v rn1 22 v rn2 22 v rn2 22 v rn2 22 v 1 5 7 9 11 13 27 25 3 2 4 6 8 10 12 14 16 18 20 22 24 26 39 28 29 30 31 32 34 35 36 37 38 40 nc nc nc j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 j8 clk clk_out +3C5d gnd +3C5d +3C5d gnd gnd c20 0.1 m f jp21 3 2 1 1 2 3 b a s2 c21 0.1 m f c43 0.1 m f gnd 32 1 jp20 gnd gnd gnd gnd c41 0.1 m f 74lvxc4245wm 74lvxc4245wm c40 0.1 m f gnd drvdd clk drvdd d5 d6 d7 d8 d9 d0 d1 d2 d3 d4 16 15 21 20 19 18 17 14 24 23 22 13 19 20 21 18 17 16 15 14 24 23 22 13 5 4 3 6 7 8 9 10 1 2 11 12 8 9 3 4 5 6 7 10 1 2 11 12 b u4 a b u4 a b u4 a b u4 a b u4 a b u4 a b u4 a b u4 a b u5 a b u5 a b u5 a b u5 a b u5 a b u5 a b u5 a b u5 a vccb vcca nc1 t/r oe oe gd2 gd1 u4 gd3 vccb vcca nc1 t/r gd2 gd1 u5 gd3 otr u1 2 710 611 5 12 drvdd 413 2 15 116 611 512 4 13 3 14 215 1 16 13 white white ad822 c42 0.1 m f 23 33 19 figure 39a. evaluation board schematic
ad9200 C19C rev. e j9 c32 0.1 f l4 tp29 +3?d c31 10/10v j2 c22 0.1 f l1 tp20 drvdd c23 10/10v j3 c24 0.1 f l2 tp21 avdd c25 33/16v j4 c26 0.1 f l3 tp22 +3?a c27 10/10v gnd j6 tp23 tp24 tp25 tp26 tp27 tp28 gnd j10 9 u6 8 11 u6 10 13 u6 12 c28 0.1 f 14 7 u6 decoupling avddclk 74ahc14 pwr u6 gnd tp1 avdd vref tp5 tp6 jp1 jp2 jp3 jp4 jp6 jp9 1 2 3 b s5 a tp7 c35 10/10v c36 0.1 f c37 0.1 f c38 0.1 f gnd gnd jp12 jp11 gnd jp13 jp7 c6 0.1 f c3 0.1 f tp3 tp4 jp10 c4 0.1 f + c5 10/10v refsense extb refbf reftf extt clampin extt refts refbs extb tp8 jp8 jp26 tp10 dcin tp9 r2 100 r3 100 a 3 b 1 2 s1 t1 c1 0.1 f c2 47/10v 6 4 3 2 1 p s ain refbs cm t1?t a 3 1 b 2 r1 49.9 s8 tp12 r51 49.9 clk tp13 dutclk r52 49.9 u6 3 4 u6 12 u6 5 6 b 1 s6 3 a 2 b 1 s7 3 a 2 r4 49.9 j1 j5 adc_clk c30 0.1 f jp22 avdd avddclk r35 4.99k r36 4.99k r34 2k avdd mode r5 10k r6 10k jp14 jp15 jp16 gnd cw figure 39b. evaluation board schematic
ad9200 C20C rev. e figure 40a. evaluation board, component signal (not to scale) figure 40b. evaluation board, solder signal (not to scale)
ad9200 C21C rev. e figure 40c. evaluation board power plane (not to scale) figure 40d. evaluation board ground plane (not to scale)
ad9200 C22C rev. e figure 40e. evaluation board component silk (not to scale) figure 40f. evaluation board solder silk (not to scale)
ad9200 C23C rev. e grounding and layout rules as is the case for any high performance device, proper ground- ing and layout techniques are essential in achieving optimal performance. the analog and digital grounds on the ad9200 have been separated to optimize the management of return currents in a system. grounds should be connected near the adc. it is recommended that a printed circuit board (pcb) of at least four layers, employing a ground plane and power planes, be used with the ad9200. the use of ground and power planes offers distinct advantages: 1. the minimization of the loop area encompassed by a signal and its return path. 2. the minimization of the impedance associated with ground and power paths. 3. the inherent distributed capacitor formed by the power plane, pcb insulation and ground plane. these characteristics result in both a reduction of electro- magnetic interference (emi) and an overall improvement in performance. it is important to design a layout that prevents noise from cou- pling onto the input signal. digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. separate analog and digital grounds should be joined together directly under the ad9200 in a solid ground plane. the power and ground return currents must be carefully managed. a general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. digital outputs each of the on-chip buffers for the ad9200 output bits (d0Cd9) is powered from the drvdd supply pins, separate from avdd. the output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy generated. in all cases, a fan-out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pf level. for drvdd = 5 v, the ad9200 output signal swing is compat- ible with both high speed cmos and ttl logic families. for ttl, the ad9200 on-chip, output drivers were designed to support several of the high speed ttl families (f, as, s). for applications where the clock rate is below 20 msps, other ttl families may be appropriate. for interfacing with lower voltage cmos logic, the ad9200 sustains 20 msps operation with drvdd = 3 v. in all cases, check your logic family data sheets for compatibility with the ad9200 digital specification table. three-state outputs the digital outputs of the ad9200 can be placed in a high impedance state by setting the three-state pin to high. this feature is provided to facilitate in-circuit testing or evaluation.
c3033eC0C8/99 printed in u.s.a. C24C ad9200 rev. e outline dimensions dimensions shown in inches and (mm). 48-lead plastic thin quad flatpack (lqfp) (st-48) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0 min 0 ?7 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09) 28-lead shrink small outline package (ssop) (rs-28) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0

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